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Ultra-Low Power VLSI design

Ultra-low power consumption is the primary design parameter in semiconductor chip designs for emerging applications such as battery-operated mobile devices and power-hungry big data servers. An efficient way for power reduction is to use low supply voltage which is near or under the threshold voltage of transistors. However, there are several technical challenges for low voltage designs. Among them, the increased sensitivity to process variation is the biggest obstacle to the low voltage design. This research attempts to address the issue by assessing the design constraints for the fundamental components in digital circuits. Based on the critical assessment, we are developing new schemes that can improve the characteristics of the fundamental components such as clocking elements and SRAM array significantly. Our specific aims in this project are (1) to propose on-chip timing error detection/correction scheme for logic pipeline, (2) to develop computer-aided-design (CAD) flow to support the proposed scheme, (3) to develop robust near-threshold on-chip SRAM array, (4) to design near-threshold CPU core. In the long-term, we plan to build ultra-low power IoT sensor node based on the IP’s we have been developing.

Integrated Circuit Design for Flexible Technologies

We aim at building flexible integrated circuit systems for wearable systems utilizing both the large area electronics based on organic device technology and high-performance electronics based on silicon device technology. 
We are currently developing techniques for improving the mobility of the organic transistor and organic circuit integration technology closely working with Prof. Sungjune Jung’s lab. Different from traditional research approaches which are mostly focused on improvement of individual transistor characteristics, we strongly believe that the key to the successful flexible system demonstration is to focus on integrated circuit perspective when we develop the organic transistor technologies. In addition to the large area organic transistor based electronic systems, we are also working on interfacing the silicon CMOS circuits to the system to utilize the high-performance flavors.

Smart Memory Design

As the data-intensive workload becomes common and speed gap between processor and memory keep growing, there is a great need to move in the selected computations to memory and/or storage. We are trying to overcome the design challenges with holistic design approach spanning device, circuit, and architecture. In addition, we are doing research of next generation memories such as STT-RAM (Spin-Transfer-Torque Magnetic RAM), PRAM(Phase Change Memory), RRAM(Resistive RAM) that are expected to overcome the scaling issues in traditional memories. Our research interests include improvement of read/write-ability, power consumption, and reliability issues. 

Neuromorphic Circuit and System Design

Neuromorphic systems basically emulates and/or simulates the behavior of biological neurons and synapses which are the main part of animals' nervous system, the brain. The brain is one of the most power-efficient computing machine. It also outperforms the traditional Von-Neumann machine in the emerging application areas like pattern recognitions. Our goal is to develop neuromorphic systems from circuit level to system level, thereby enabling computers to handle cognitive functions more power-efficient and fast. We are also trying to develop off and on-line learning algorithms to apply them to real-time processing of massive data. Target applications include spatio-temporal pattern recognition and efficient distributed sensor system.	

SNN Core

※ Lab Safety Manuals

1. DICE LAB 연구실 안전 운영 지침서
2. DICE LAB 우수 연구실 안전 환경 시스템 메뉴얼
3. 포스텍 연구실 안전 관리 규정
4. 사고 대응 메뉴얼
5. 지진 대피 메뉴얼
6. 안전관리 우수연구실 인증서