Publications

  • 2019
  • 2018
  • 2017
  • 2016
    • Journal
      • H. Yoo, M, Ghittorelli, E. C. Smits, G. H. Gelinck, H. Lee, F. Torricelli, J-J. Kim, “Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors,” Scientific Reports , 6, 35585; doi: 10.1038/srep35585 Oct. 2016
      • H. Yoo, E. C. Smits, A. J. van Breeman, J-L. van der Steen, F. Torricelli, M, Ghittorelli, J. Lee, G. H. Gelinck, J-J. Kim, “Asymmetric Split-Gate Ambipolar Transistor and Its Circuit Application to Complementary Inverter,” Advanced Materials Technologies, vol. 1, Issue 4. July 2016.
      • J. Kwon, S. Kyung, S. Yoon, J-J. Kim and S. Jung, “Solution-processed vertically stacked complementary organic circuits with inkjet-printed routing,” Advanced Science, Vol. 3, Issue 5, May 2016
      • Insup Shin, Jae-Joon Kim, Yu-Shiang Lin and Youngsoo Shin, “One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements,” IEEE Transactions on VLSI Systems, Vol. 24, No. 2, pp 600-612, Feb. 2016.
    • Conference
      • Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungju Yoo, Jae-Joon Kim “Area-Efficient One-Cycle Correction Scheme for Timing Errors in Flip-Flop Based Pipelines,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.137-140, Nov. 2016.
  • 2015
    • Journal
      • Hocheon Yoo*,Hyun Ho Choi*,Tae Joo Shin, Taiuk Rim, Kilwon Cho, Sungjune Jung, and Jae-Joon Kim, “Self-Assembled, Millimeter-Sized TIPS-Pentacene Spherulites Grown on Partially Crosslinked Polymer Gate Dielectric”, Adv. Funct. Mater. 2015, 25, 3658 (*equally contributed)
      • Insup Shin, Jae-Joon Kim, and Youngsoo Shin, “Aggressive voltage scaling through fast correction of multiple errors with seamless pipeline operation,” IEEE Transactions on Circuits and Systems I, vol. 62, no. 2, pp. 468-477, Feb. 2015
  • 2014
    • Conference
      • Hayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee “Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs,” Design Automation and Test in Europe (DATE), Mar. 2014.
      • Insup Shin, Jae-Joon Kim, Youngsoo Shin, “Power Minimization of Pipeline Architecture through 1-Cycle Error Correction and Voltage Scaling,” IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), pp.179-184, Jan. 2014.
  • 2013
    • Journal
      • Amlan Ghosh, Rahul Rao, Jae-Joon Kim, Ching-Te Chuang, Richard Brown, “Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection,,” IEEE Trans. on VLSI Systems, Vol. 21, No. 9, pp 1683-1692, Sep. 2013.
    • Conference
      • Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin, “A Pipeline Architecture with 1-Cycle Timing Error Correction for Low Voltage Operations,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp.199-204, Sep. 2013.
  • 2012
    • Conference
      • Aditya Bansal, Jae-Joon Kim, Rahul Rao, “Usage-Based Degradation of SRAM Array due to Bias Temperature Instability,” IEEE International Reliability Physics Symposium (IRPS), pp. 2F.6.1 – 2F.6.4, 2012.
  • 2011
    • Journal
      • Ik-Joon Chang, Jae-Joon Kim, Keejong Kim and Kaushik Roy, “Robust Level Converter Design for Sub-theshold/Super-Threshold Operation: 100mV to 2.5V,” IEEE Trans. on VLSI Systems Vol. 19, No. 8, pp 1429-1437, Aug. 2011.
      • Saibal Mukhopadyay, Rahul Rao, Jae-Joon Kim, and Ching-Te Chuang , “SRAM Write-Ability Improvement with Transient Negative Bit-Line Voltage”, IEEE Trans. on VLSI Systems Vol. 19, No. 1, pp 24-32, Jan. 2011.
    • Conference
      • Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. P. Griffin, and Kaushik Roy, “Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors,” International Symposium on Low Power Electronics and Design (ISLPED), pp. 303-308, Aug. 2011.
      • Jae-Joon Kim, Rahul Rao, Jeremy Schaub, Amlan Ghosh, Aditya Bansal, Kai Zhao, Barry Linder, James Stathis, “PBTI/NBTI Monitoring Ring Oscillator Circuits with On-Chip Vt Characterization and High Frequency AC Stress Capability,” Symposium on VLSI Circuits, pp. 224-225, Jun. 2011.
      • Jae-Joon Kim, Barry Linder, Rahul Rao, Tae-Hyoung Kim, Pong-Fei Lu, Keith Jenkins, Chris H Kim, Aditya Bansal, Saibal Mukhopadyay and Ching-Te Chuang, “Reliability Monitoring Ring Oscillator Structures for Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies,” IEEE International Reliability Physics Symposium (IRPS), pp. 2B.4.1-2B.4.4, Apr. 2011.
      • Aditya Bansal, Kai Zhao, Jae-Joon Kim and Rahul Rao, “Bias Temperature Instability Model for Digital Circuits Predicting Instantaneous FET Response,” IEEE International Reliability Physics Symposium (IRPS), pp. CR.2.1-CR.2.4, Apr. 2011.
      • D. Ioannou, K. Zhao, A. Bansal, B. Linder, R. Bolam, E. Cartier, J. Kim, R. Rao, G. La Rosa, G. Massey, M. Hauser, K. Das, J. Stathis, J. Aitken, D. Badami, S. Mittl, “A robust reliability methodology for accurately predicting Bias Temperature Instability Induced Circuit Performance Degradation in HKMG CMOS,” IEEE International Reliability Physics Symposium (IRPS), pp. CR.1.1-CR.1.4, Apr. 2011.
  • 2010
    • Journal
      • Niladri Mozumder, Saibal Mukhopadyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy, “Self-Repairing SRAM Using On-Chip Detection and Compensation”, IEEE Trans. on VLSI Systems Vol. 18, No. 1, pp 75-84, Jan. 2010.
    • Conference
      • Jae-Joon Kim, Rahul Rao, Keunwoo Kim, “Technology-Circuit Co-Design of Asymmetric SRAM Cells for Read Stability Improvement,” IEEE Custom Circuit Integrated Circuits Conference (CICC), Sep. 2010.
  • 2009
    • Journal
      • Rahul Rao, Keith Jenkins, and Jae-Joon Kim, “A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry”, IEEE Journal of Solid State Circuits, Vol. 44, No.9, pp 650-658, Sep. 2009
      • Jae-Joon Kim, Aditya Bansal, Rahul Rao, Shih-Hsien Lo, and Ching-Te Chuang, “Relaxing Conflict Between Read Stability and Write-ability in 6T SRAM Cell using Asymmetric Transistors,” IEEE Electron Device Letters, Vol. 30, No.8, pp 852-854, Aug. 2009.
      • Aditya Bansal, Rahul Rao, Jae-Joon Kim, Sufi Jafa, James Stathis, and Ching-Te Chuang, ” Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability,” Microelectronics Reliability, Vol. 49, pp. 642-649, 2009.
      • Ik-Joon Chang, Jae-Joon Kim, Sang Phil Park and Kaushik Roy, “32kb 10T Sub-threshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS,” IEEE Journal of Solid State Circuits, Vol. 44, No.2, pp 650-658, Feb. 2009
    • Conference
      • Aditya Bansal, Rahul Rao, Jae-Joon Kim, Sufi. Jafa, James Stathis, and Ching-Te Chuang, ” Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance”, IEEE International Reliability Physics Symposium (IRPS), pp. 745-749, May 2009
      • Jae-Joon Kim, Rahul Rao, Saibal Mukhopadyay, and Ching-Te Chuang, “Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects,” IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), pp. 163 -166, June 2008.
  • 2008
    • Journal
      • Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, and Kaushik Roy, “Optimal Dual-Vt Design in Sub-100 Nanometer PD/SOI and Double-Gate Technologies ,” IEEE Trans. on Electron Devices, Vol. 55, No.5, pp 1161-1169, May. 2008.
    • Conference
      • Saibal Mukhopadyay, Rahul Rao, Jae-Joon Kim, and Ching-Te Chuang , “Capacitive Coupling Based Transient Negative Bit-Line Voltage (Tran-NBL) Scheme for Improving Write-Ability of SRAM Design in Nanometer Technologies”, IEEE International Symposium on Circuits and Systems (ISCAS), pp.18-21, May 2008.
      • Niladri Mozumder, Saibal Mukhopadyay, Jae-Joon Kim, and Ching-Te Chuang and Kaushik Roy, “Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry,” IEEE VLSI Test Symposium, pp. 101-106, Apr. 2008.
      • Ik-Joon Chang, Jae-Joon Kim, Sang Phil Park and Kaushik Roy, “A 32kb 10T Subthreshold SRAM Array with Bit-interleaving and Differential Read Scheme in 90nm CMOS,” International Solid-State Circuit Conference (ISSCC), pp. 388-389, Feb. 2008.
      • Rahul Rao, Keith Jenkins, and Jae-Joon Kim, “A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement”, International Solid-State Circuit Conference (ISSCC), pp. 412-413, Feb. 2008.
      • Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadyay, Ching-Te Chuang, and Kaushik Roy, “Optimal Dual-Vt Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies,” Proceedings of International Conference on VLSI Design, pp. 125-130, Jan. 2008
      • Amlan Ghosh, Rahul Rao, Jae-Joon Kim, Ching-Te Chuang, and Richard Brown,” On-Chip Process Variation Detection using Slew-Rate Monitoring Circuit in Sub-100nm CMOS Technology”, Proceedings of International Conference on VLSI Design, pp. 143-147, Jan. 2008.
  • 2007
    • Journal
      • Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv Joshi, Ching-Te Chuang, and Kaushik Roy, “Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices,” Microelectronics Journal, vol. 38, pp. 931-941, 2007.
    • Conference
      • Ching-Te Chuang, Saibal Mukhopadyay, Jae-Joon Kim, Keunwoo Kim, and Rahul Rao, “High-Performance SRAM in Nanoscale CMOS: Design Challenges and Techniques,”, (Invited Plenary Paper), IEEE International Workshop on Memory Technology, Design, and Testing, pp. 4-12, Dec. 2007.
      • Rahul Rao, Jae-Joon Kim, and Ching-Te Chuang, “Evaluation and Optimization of FinFET Quantization Error in Porting a Design from Planar Silicon Technology,” Proceedings of IEEE International SOI Conference, pp. 49-50, Oct. 2007.
      • Rahul Rao, Aditya Bansal, Jae-Joon Kim, Ching-Te Chuang, and Kaushik Roy, “Accurate Modeling and Analysis of Currents in Trapezoidal FinFET Devices,” Proceedings of IEEE International SOI Conference, pp. 47-48, Oct. 2007.
      • Aditya Bansal, Keunwoo Kim, Jae-Joon Kim, Saibal Mukhopadyay, Ching-Te Chuang, and Kaushik Roy, “High Performance Device Optimization and Dual-Vt Technology Options for Double Gate FET” International Conference on IC Design and Technology (ICICDT), pp.83-86, May 2007
      • Keunwoo Kim, Jae-Joon Kim, and Ching-Te Chuang, “Asymmetrical SRAM Cells with Enhanced Read and Write Margins,” International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), pp. 162-163, Apr. 2007.
  • 2006
    • Journal
      • Jae-Joon Kim and Kaushik Roy, “A Low Swing Circuit Style for Leakage Tolerannce in Partially Depleted Silicon-on-Insulator CMOS Technologies,” IEEE Trans. on VLSI Systems Vol. 14, No. 5, pp 549-552, May 2006.
      • Chris H. Kim, Jae-Joon Kim, Ik-Joon Chang and Kaushik Roy, “PVT-Aware Leakage Reduction for On-Die Caches with Improved Read Stability,” IEEE Journal of Solid State Circuits. Vol. 41, No.1, pp 170-178, Jan. 2006
    • Conference
      • Ik-Joon Chang, Jae-Joon Kim, and Kaushik Roy, “Robust Level Converter Design for Sub-threshold Logic,” 2006 International Symposium on Low Power Electronics and Design (ISLPED), pp. 14-19, Oct. 2006.
      • Jae-Joon Kim, Keunwoo Kim, and Ching-Te Chuang, “Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability,” 2006 European Solid-State Circuit Conference (ESSCIRC), pp. 74-77, Sep. 2006.
  • 2005
    • Journal
      • Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, and Kaushik Roy, “A Forward Body-Biased Low-Leakage SRAM Cache: Device, Circuit and Architecture Considerations,” IEEE Trans. on VLSI Systems Vol. 13, No.3, pp 349-357, Mar. 2005.
    • Conference
      • Jae-Joon Kim, Keunwoo Kim, and Ching-Te Chuang, “Back-Gate Controlled READ SRAM Design with Improved Stability,” 2005 IEEE International SOI Conference, pp. 97-98, Oct. 2005.
      • Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv Joshi, Ching-Te Chuang, and Kaushik Roy, “Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits,” Proceeding of International Symposium on Quality Electronics Design (ISQED), pp. 410-415, Mar. 2005.
      • Chris H. Kim, Jae-Joon Kim, Ik-Joon Chang and Kaushik Roy, “PVT-Aware Leakage Reduction for On-Die Caches with Improved Read Stability,” Proceeding of International Solid-State Circuit Conference (ISSCC), pp. 69-70, Feb. 2005.
  • 2004
    • Journal
      • Jae-Joon Kim and Kaushik Roy, “Double Gate MOSFET Subthreshold Circuit for Ultra-Low Power Applications,” IEEE Trans. on Electron Devices, Vol. 51, No.9, pp 1468-1474, Sep. 2004.
    • Conference
      • Chris H. Kim, Hari Ananthanarayanan, Jae-Joon Kim and Kaushik Roy, “Effectiveness of using Supply Voltage as Back-Gate Bias in Ground Plane SOI MOSFETs,” IEEE International SOI Conference, pp. 69-70, Oct. 2004.
  • 2003
    • Conference
      • Jae-Joon Kim and Kaushik Roy, “Double Gate MOSFET Subthreshold Logic for Ultra-Low Power Applications,” 2003 IEEE International SOI Conference, pp. 97-98, Sep. 2003.
      • Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, and Kaushik Roy, “A Forward Body-Biased Low-Leakage SRAM: Device and Architecture Considerations,” International Symposium on Low Power Electronics and Design (ISLPED), pp. 6-9, Aug. 2003.
  • 2002
    • Conference
      • Jae-Joon Kim and Kaushik Roy, “SOI-Specific Tri-State Inverter and its Application,” 2002 IEEE International SOI Conference, pp. 145-146, Oct. 2002.
      • Jae-Joon Kim and Kaushik Roy, “Sense-Amplifierless DCSL: A Circuit Style Tolerant to Floating Body Effects in PD/SOI,” 28th European Solid State Circuit Conference (ESSCIRC), pp. 271-274, Sep. 2002.
      • Jae-Joon Kim, Rajiv Joshi, Ching-Te Chuang, and Kaushik Roy, “SOI-Optimized 64-bit High-Speed CMOS Adder Design,” 2002 Symposium on VLSI Circuits (SOVC), pp.122-125, Jun. 2002.
  • 2001
    • Conference
      • Jae-Joon Kim and Kaushik Roy, “A Leakage Tolerant High Fan-in Dynamic Circuit Design Technique,” 27th European Solid State Circuit Conference (ESSCIRC), pp.324-327, Sep. 2001.
  • 1999
    • Journal
      • Sung-Joon Hong, Jae-Joon Kim, Young-June Park , and Hong-Shick Min, “Analysis of the spurious negative resistance of PN junction avalanche breakdown,” IEEE Trans. on Electron Devices, Vol. 46, No.1, pp 230-236, Jan. 1999.
  • 1997
    • Conference
      • Jae-Joon Kim, Sung-Joon Hong, Young-June Park, and Hong-Shick Min, “A new carrier mobility model using the second and the fourth moment of the Boltzmann Transport Equation,” the International Semiconductor Device Research Symp.(ISDRS), Dec. 1997.